https://s100computers.com/Hardware%20Folder/NorthStar/FP%20B...
The microcode is available, so it would be a fun project to write a simulator that runs the microcode.
Manual and schematics are here if anyone is looking for them: https://bitsavers.org/pdf/northstar/boards/North_Star_Floati...
(I'm the guy behind the wang2200.org domain)
A cheap mobile phone CPU+GPU costs the manufacturer maybe $20, and typically does 50 GFLOPS on the CPU and 500+ on the GPU. So 10 million times the performance for 1/25th the cost.
Humbling too how "worthless" all the incredible ingenuity of the 8087 circuits and die designs now is, although I'm sure many of those innovations live on in modern chips.
The article mentions it already has a two-stage design, shifting bits and then bytes, so it can't be about shifting more than one bit at a time. Anyone know why?
If you're using MOS pass transistors for each stage, you lose some voltage at each stage, which limits the number of stages. I think this is why the 8087 (and the 386) used two-stage shifters rather than logarithmic shifters. I don't know how the circuit area compares between the two approaches--two more complex stages vs six simpler stages--but I suspect the two-stage approach wins.
I sometimes wonder if some design decisions were made on that basis.
You might think that the 8087's shifter would be a regular grid, easy to lay out by hand. It turns out to be very optimized and irregular. (I traced it out by hand and it was a pain.)
https://news.ycombinator.com/item?id=48519011 (about the 8087's adder)
https://www.righto.com/2020/05/die-analysis-of-8087-math-cop...
https://www.righto.com/2026/06/intel-8087-adder-reverse-engi...
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Analysis of the 8087 math coprocessor's fast bit shifter,
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